James Dwain Hunkins

E-Mail: jhunkins@pacbell.net

(650) 701-0434 (home)

 

CAREER OBJECTIVE	Project/team management mixed with electronic design. Interests in system architecture, high speed logic, graphics and multimedia, embedded controllers, board and chip design. Using both hardware and software experience to manage a project and perform engineering functions.
DESIGN EXPERIENCE
Pro Desktop Senior Team Engineer IMAC Development    Technology Lead    Apple Computer, Inc. 12/99 - Present	Senior team member in charge of graphics card development for multiple projects. Also general contribution to architecture, manufacturing issues, and different sectional designs. Technology Lead for one of the next generation IMAC - responsible for coordinating an IMAC design team - more to come
Board Development    Sen Member Technical Staff    Raycer, Inc.    4/98 - 11/99	Member of senior engineering staff  - participated in full project management and feature trade off decisions  - worked on future product planning  - supported marketing efforts Designed one of the first 110W AGP Pro cards for the WTX workstations  - set up board development environment (team, tools, lab)  - managed one person internally and directed four people/groups externally  - high speed signals (800 Mbps - Rambus, 330 MHz - chip to chip signaling)  - ultra high routing density including length matching  - over 1000 components in a 14"x4" area  - 21 PLL/DLLs in the system  - 180/360 MBytes of Rambus (populated both sides)   - AGP 4x interface into a custom chip  - layout included extensive pre-layout design, developing full layout rules, and    working in parallel with an external group  - designed power scheme with 6 voltages on the single card  - co-developed high efficiency 85 W 2.5V voltage regulator  - worked with external signal integrity group to optimize signal integrity,    including cross talk, reflections, and EMI issues  - worked closely with Rambus during their early development efforts Designed three custom chip pin assignments; 624 pin CBGA packages  - matched to internal chip layout structure  - developed breakouts of up to 14 balls deep in 4 layers  - optimized to minimize layer crossing and external length compensation  - worked with chip designers and external package layout engineer Joint development with chip designers on  - reset and clocking schemes (board and chip level)  - chip debug protocols and methodology including chip-to-chip signal testing  - debug and bring up plans
Arcade Platform Development    Staff Electrical Engineer    Acclaim Coin-Op Ent    10/95 - 3/98	Architected, designed, debugged, and brought to production new high performance 3D graphics arcade platform motherboard  - two CPLD/FPGA parts designed in VHDL/schematics  - multiple high load buses  - custom compressed DMA type controllers  - parallel operation of different hardware units  - hardware/software optimization to boost individual and parallel performances  - 200 MHz R5000 and dual 3DFX chip sets with memory/video circuitry  - controlled layout, termination and noise control  - interfaces to external devices (custom Sound/IO card, IDE, Firewire, serial)  - design of custom add-on card high performance interface  - included debug experience of proprietary JPEG/filter PCI slot card  - writing of test code and debugging startup/game code Designed three memory/IO add-on cards for two separate platforms  - reverse engineering to understand externally designed platform interface  - interface to external sound card  - static discharge protection and grounding control  - completed all three cards and set up infrastructure of new group in one year Coordinated the work of several people; design, support, test, and manufacturing. This included training junior engineers and a technician.
New Product Development    Senior Electrical Engineer    Phoenix Precision Graphics    01/93 - 10/95	Designed and debugged main digital embedded control board for large format color printer/plotter  - three CPLD/FPGA parts designed in HDL  - innovative data rotation/double buffer for translating data formats in hardware  - hardware/software optimizations to compensate for bus limitations of R3041  - multiple interfaces to other system cards and external devices  - writing test code and several development software tools Architected and built a high speed interchangeable multiple interface I/O card  - required special filtering to compensate for wide variety of external drive    capabilities and ground variances
Epson Research Center    Graphics Hardware Eng    Epson Portland, Inc.    10/91 - 12/92	Developed and debugged a High Speed Local (HSL) bus extension to an existing high-end PC platform with changeable CPU cards Designed and completed an advanced frame buffer card for the HSL bus  - resolutions up to 1280x1024 / 8 bit color at 75 Hz refresh  - double sided, high density card with 27 EPLDs (up to -4 speeds)  - used VRAM special features to add graphics accelerations Represented EPSON at VESA local bus committee meetings
i860 Platform Group    Systems Hardware Eng    Intel Corporation    12/89 - 10/91	Designed and simulated I/O section of Intel's i860XP reference platform  - bus conversions to intelligent LAN and SCSI co-processors  - integrated components of the Intel EISA DT chip set Analyzed the original i860XR workstation architecture and reviewed the design with external Japanese design partner Established and maintained CAD environment for i860 Platform Group  - included choice, installation, running and troubleshooting of tools  - hired and supervised system administrator
Advanced Technology    Electrical Engineer    Unisys Corporation    5/88 - 11/89	Designed and debugged i860XR (A1 stepping) evaluation card with variable wait states under a one month time constraint Devised and tested circuits for interfacing floating point co-processors Debugged TS34020 PC high speed video add-on card Developed, wrote and ported assembly code floating point benchmarks for various RISC and CISC processors
EDUCATION	B.S. In Electrical Engineering  [5/88] B.S. In Computer Science  [5/88]    South Dakota School of Mines and Technology
TOOLS	Software Languages - C, C++, assembly Layout - Cadence Allegro and Specctra Schematic Entry - Concept, ViewLogic, Orcad, Valid Simulation - ViewLogic, Orcad, Valid, VHDL/HDL languages, Spice CPLD/FPGA design - Xilinx, Altera, Minc (schematic, Verilog, VHDL) Project Management - Microsoft Project
WRITING	Contributor to different QL special interest publications Multiple specs and design guides (hardware and software)
OTHER INTERESTS	Developed small software utilities for QL, OS/2, DOS, and Windows 3.1  - released BBS Mail Reader for QL  - several small tools for internal use at Raycer, Acclaim and Phoenix Active member of QL (European computer) international group Hobbies include skiing, biking, working out, science fiction, and software
REFERENCES	Available on Request